lmbench/lat-mem-rd

Memory read latency benchmark sweeping working-set size and stride across the memory hierarchy.

Benchmark Profile

  • Type: Micro

  • Kernel subsystem: Memory management, cache/TLB behavior

  • Coverage: Directly measured

  • Topology: Single role: executer

Overview

lat-mem-rd measures sequential and random read latency across the memory hierarchy (L1/L2/L3 caches and main memory) for a range of working-set sizes and access strides. It helps identify cache capacity boundaries and memory controller behaviour differences across SUT configurations.

Fastpath Parameters

Name

Description

parallel

Number of parallel lat-mem-rd processes to run (-p flag). Mandatory.

repeat

Number of measurement repetitions per data point (-r flag). Mandatory.

work-set-size-start

Sweep start value for working-set size in MB. Mandatory.

work-set-size-end

Sweep end value for working-set size in MB. Optional; defaults to 256.

work-set-size-multiply

Multiplicative sweep step for working-set size. Optional; defaults to 4.

work-set-strides

Access stride in bytes. Can be a single value or comma-separated list. Mandatory.

work-set-random

Enable random access (-t flag). One of: enabled, disabled, both. Mandatory.

Result Classes

Result class names encode the stride and working-set size, for example ‘Stride: 128 Size: 4 MB’. The improvement direction is lower-is-better (latency).

Fastpath Metadata

Field

Value

Suite

lmbench

Name

lat-mem-rd

Type

memory

Container Image

registry.gitlab.arm.com/tooling/fastpath/containers/lmbench:v1.0

Documentation Path

documentation/user-guide/benchmarkcatalog/lmbench-lat-mem-rd.rst

Documentation URL

https://fastpath.docs.arm.com/user-guide/benchmarkcatalog/lmbench-lat-mem-rd.html